The present invention relates to a process for manufacturing a multi-layer circuit board and a multi-layer circuit board manufactured according to this process.
A conventional technique for obtaining circuit boards with all interapaces between the components which are mounted on the surface of the circuit board, in other words circuit boards having a high so-called packing density, is to produce the circuit board as a multi-layer board. A multi-layer circuit board comprises a plurality of supporting layers of non-conducting material on which a conducting pattern is arranged. The conducting patterns on the various supporting layers are connected to one another in desired fashion through the creation of holes, so called xe2x80x9cvia-holesxe2x80x9d, between the various supporting layers at the locations in which connection is required. The via-holes are made electrically conducting by being wholly or partially filled with electrically conducting material.
A known technique for joining together the various supporting layers in a multi-layer circuit board is by so-called xe2x80x9cfusion bondingxe2x80x9d. This means that the conducting patterns are arranged on the various supporting layers, and the various layers are arranged one on top of the other in desired fashion, subsequent to which the structure which is thus formed is exposed to a temperature in excess of the melting point for the material in the supporting structure. A problem which arises in this process is that when the supporting layers reach or exceed their melting point, the forms of the conducting patterns can alter due to movements in the supporting layers. When the supporting layer then stiffens, the conducting patterns might therefore not have precisely the same form which they had earlier.
Because of the above-described problem, the conducting patterns often have to be made wider than required in order to ensure that the desired region is covered by conducting patterns. This adds to the difficulty of producing circuit boards with small conducting patterns and small intervals between the conducting patterns.
An alternatively previously known technique in fusion bonding is to place between the supporting layers materials which have a lower melting point than the supporting layers. When heated, the structure will thus be joined together without the structure of the conducting patterns being affected by dimensional changes in the supporting layers. This technique leads however to increased manufacturing costs, and results in the height of the structure becoming greater than desired.
Japanese patent document JP 63 047127 describes a method for manufacturing circuit boards which is based upon a number of basically identically structured laminates being joined together one on top of the other. Each laminate comprises a core which, on its upper and lower side, is surrounded by an outer material with lower melting point than the core. The laminate is heated to a temperature which exceeds the melting point of the outer material but is lower than the melting point of the core. The various strata of the laminate are thus made to fasten together.
A drawback with this method seems to be that each supporting stratum has to be surrounded by two other strata, whose only real function is that of adhesive layers. Japanese patent document JP 01 025597 shows a method in which supporting layers are surrounded by various types of paste with different melting points. This method appears to lead to higher material costs and multiple stages in the production of the circuit boards.
Document WO 96/08945 shows a method which is typical of the method using various strata whose only function is that of adhesive layers.
The problem which is solved by the present invention is thus to achieve a method for manufacturing multi-layer circuit boards, which method is cheap and simple to use, and allows the various supporting layers in the board to be fastened in place without adhesive strata or other intermediate strata.
The invention solves this problem through a process for manufacturing a multi-layer circuit board comprising a plurality of supporting layers for conducting patterns, in which the supporting layers are all of different materials. As material for a first supporting layer for conducting patterns, that material is chosen which has the highest melting point of the different materials for supporting layers for conducting patterns. On this first supporting layer there is arranged a first conducting pattern Of desired shape.
Starting from the first supporting layer, new supporting layers are arranged successively in which, as material for each new supporting layer, a material is chosen with lower melting point than the supporting layer which is closest in the direction of the first supporting layer. Each new supporting layer is attached to the structure by exposing the structure to a temperature which exceeds the melting point of the new supporting layer but is lower than the melting point for the supporting layer which is closest in the direction of the first supporting layer. In this way, the conducting patterns present in the structure will not be affected by movements in their respective supporting layers.
Once the structure, after each heating, has regained a temperature which allows the new uppermost supporting layer to be worked, a conducting pattern of desired shape is created on at least one side of the new uppermost supporting layer.
Electrically conducting patterns in at least two supporting layers are connected to each other. These connections are preferably constituted by via-holes.
The process is repeated until the desired number of layers are present in the structure. On the uppermost layer, conducting patterns and/or electronics components can be arranged.